7.13~7.37 GHz宽带锁相跳频源的设计与实现
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国家自然科学基金资助项目(61164020);赣州市社会科学研究课题基金资助项目(13045,13047);江西理工大学应用科学学院科研基金课题资助项目

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Design and Implementation of an 7.13~7.37 GHz Wideband Frequency Hopping Source Base on PLL
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    摘要:

    设计了一种采用电荷泵锁相技术的7.13~7.37 GHz宽带跳频信号源,采用复杂可编程逻辑器件(CPLD)控制电荷泵锁相环(CPPLL)频综芯片ADF4108产生跳频信号,跳频带宽高达240 MHz,输出功率约10 dBm,电平波动为0.7 dB,杂散抑制<-70 dBc,输出端采用六阶微带低通滤波器进行带外谐波抑制,二次谐波抑制<-60 dBc,传输速率快,电路模块结构紧凑。实验结果表明,所设计的跳频宽带信号源具有快跳变,低相噪,低杂散,高可靠性及高稳定度等优点。

    Abstract:

    In this paper, a 7.13~7.37 GHz wideband frequency hopping source base on PLL theory is introduced.The charge pump phase locking loop(CPPLL) chip ADF4108 which produce frequency hopping signal is controlled by complex programmable logic device(CPLD).The bandwidth of the system is high to 240 MHz,The output signal power is about 10 dBm,and the level fluctuation is 0.7 dB.Spur restraining is less than -70 dBc.The 6th order micro strip low pass filters using in the output of the module which with high data speed and small area.And then the two order harmonic suppression is less than -60 dBc.The test data show that the hopping frequency synthesizer has good performance, such as low jumping time,high spur restraining,low phase noise and high stability.

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邓茜,梁小朋.7.13~7.37 GHz宽带锁相跳频源的设计与实现[J].压电与声光,2015,37(1):84-87. DENG Qian, LIANG Xiaopeng. Design and Implementation of an 7.13~7.37 GHz Wideband Frequency Hopping Source Base on PLL[J]. PIEZOELECTRICS AND ACOUSTOOPTICS

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  • 在线发布日期: 2015-01-22
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